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1 data sheet acquired from harris semiconductor schs206b features synchronous programmable n counter n = 3 to 9999 or 15999 presettable down-counter fully static operation mode-select control of initial decade counting function ( 10, 8, 5, 4, 2) master preset initialization latchable n output fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v applications communications digital frequency synthesizers; vhf, uhf, fm, am, etc. fixed or programmable frequency division ?ime out timer for consumer-application industrial controls description the ?c4059 are high-speed silicon-gate devices that are pin-compatible with the cd4059a devices of the cd4000b series. these devices are divide-by-n down-counters that can be programmed to divide an input frequency by any number ? from 3 to 15,999. the output signal is a pulse one clock cycle wide occurring at a rate equal to the input frequency divide by n. the down-counter is preset by means of 16 jam inputs. the three mode-select inputs k a ,k b and k c determine the modulus (?ivide-by number) of the first and last counting sections in accordance with the truth table. every time the first (fastest) counting section goes through one cycle, it reduces by 1 the number that has been preset (jammed) into the three decades of the intermediate counting section an the last counting section, which consists of flip-flops that are not needed for opening the first counting section. for example, in the 2 mode, only one flip-flop is needed in the first counting section. therefore the last counting section has three flip-flops that can be preset to a maximum count of seven with a place value of thousands. if 10 is desired for the first section, k a is set ?igh? k b ?igh and k c ?ow? jam inputs j1, j2, j3, and j4 are used to preset the first counting section and there is no last counting section. the intermediate counting section consists of three cascaded bcd decade ( 10) counters presettable by means of jam inputs j5 through j16. the mode-select inputs permit frequency-synthesizer channel separations of 10, 12.5, 20, 25 or 50 parts. these inputs set the maximum value of n at 9999 (when the ?st counting section divides by 5 or 10) or 15,999 (when the ?st counting section divides by 8, 4, or 2). the three decades of the intermediate counter can be preset to a binary 15 instead of a binary 9, while their place values are still 1, 10, and 100, multiplied by the number of the n mode. for example, in the 8 mode, the number from which counting down begins can be preset to: 3rd decade 1500 2nd decade 150 1st decade 15 last counting section 1000 the total of these numbers (2665) times 8 equals 12,320. the ?st counting section can be preset to 7. therefore, 21,327 is the maximum possible count in the 8 mode. the highest count of the various modes is shown in the extended counter range column. control inputs k b and k c can be used to initiate and lock the counter in the ?aster preset state. in this condition the flip-flops in the counter are preset in accordance with the jam inputs and the counter remains in that state as long as k b and k c both remain low. the counter begins to count down from the preset state when a counting mode other than the master preset mode is selected. ordering information part number temp. range ( o c) package cd54hc4059f3a -55 to 125 24 ld cerdip cd74hc4059e -55 to 125 24 ld pdip cd74hc4059m96 -55 to 125 24 ld soic note: when ordering, use the entire part number. the suf? 96 denotes tape and reel. february 1998 - revised may 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated cd54hc4059, cd74hc4059 high-speed cmos logic cmos programmable divide-by-n counter [ /title (cd74 hc4059 ) / sub- j ect (high- speed cmos logic cmos pro-
2 the counter should always be put in the master preset mode before the 5 mode is selected. whenever the master preset mode is used, control signals k b = ?ow and k c = ?ow must be applied for at least 3 full clock pulses. after preset mode inputs have been changed to one of the modes, the next positive-going clock transition changes an internal ?p-?p so that the countdown can begin at the second positive-going clock transition. thus, after an mp (master preset) mode, there is always one extra count before the output goes high. figure 1 illustrates a total count of 3 ( 8 mode). if the master preset mode is started two clock cycles or less before an output pulse, the output pulse will appear at the time due. if the master preset mode is not used, the counter jumps back to the ?am count when the output pulse appears. a ?igh on the latch enable input will cause the counter output to remain high once an output pulse occurs, and to remain in the high state until the latch input returns to ?ow? if the latch enable is ?ow? the output pulse will remain high for only one cycle of the clock-input signal. pinout cd54hc4059 (cerdip) cd74hc4059 (pdip, soic) top view functional diagram 1 2 3 4 5 6 7 8 9 10 11 12 cp le j1 j2 j3 j4 j16 j15 j14 j13 k c gnd 16 17 18 19 20 21 22 23 24 15 14 13 v cc j5 j6 j7 j8 j10 j12 k a k b q j9 j11 q = k c le k b k a cp j1 - j16 f in n ------- ?? ?? truth table mode select input first counting section last counting section counter range design extended k a k b k c mode divides-by can be preset to a max of: (note 1) jam inputs used: mode divides-by can be preset to a max of: (note 1) jam inputs used: max max h h h 2 1 j1 8 7 j2, j3, j4 15,999 17,331 l h h 4 3 j1, j2 4 3 j3, j4 15,999 18,663 hlh 5 (note 2) 4 j1, j2, j3 2 1 j4 9,999 13,329 l l h 8 7 j1, j2, j3 2 1 j4 15,999 21,327 h h l 10 9 j1, j2, j3, j4 1 0 - 9,999 16,659 x l l master preset master preset - - x = don? care notes: 1. j1 = least signi?ant bit. j4 = most signi?ant bit. 2. operation in the 5mode (1st counting section) requires going through the master preset mode prior to going into the 5mode. at power turn-on, kc must be ?ow?for a period of 3 input clock pulses after vcc reaches a minimum of 3v. cd54hc4059, cd74hc4059 cd54hc4059, cd74hc4059
3 how to preset the hc/hct4059 to desired n the value n is determined as follows: to calculate preset values for any n count, divide the n count by the mode. the resultant is the corresponding preset values of the 5th through 2nd decade with the remainder being equal to the 1st decade value. note: to verify the results, use equation 1: n = 5 (1000 x 1 + 100 x 6 + 10 x 9 + 1 x 5) + 4 n = 8479 n = (mode ? ) (1000 x decade 5 preset + 100 x decade 4 preset + 10 x decade 3 preset + 1 x decade 2 preset) + decade 1 preset ? mode = first counting section divider (10, 8, 5, 4 or 2) (eq. 1) preset value = n mode example: n = 8479, mode = 5 1695 + 4 (preset values) 5 | 8479 mode n mode select = 5 k a k b k c hlh (eq. 2) program jam inputs (bcd) j1 j2 j3 j4 l lh h 41 j5 j6 j7 j8 h lhl 5 j9 j10 j11 j12 hllh 9 j13 j14 j15 j16 lhhl 6 figure 1. functional block diagram first counting section 10, 8, 5, 4, 2 last counting section 1, 2, 2, 4, 8 10 10 10 recognition gating preset enable intermediate counting section output stage mode control presettable logic gnd v cc 12 24 clock 1 input mode 14 13 11 k a k b k c select inputs latch 2 enable divide-by-n 23 output p.e. j1 3 j2 4 j3 5 j4 6 j5 22 j6 21 j7 20 j8 19 j9 18 j10 17 j11 16 j12 15 j13 10 j14 9 j15 8 j16 7 program jam inputs (bcd) cd54hc4059, cd74hc4059 cd54hc4059, cd74hc4059
4 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical) ja ( o c/w) e (pdip) package (note 3) . . . . . . . . . . . . . . . . . . . 67 m (soic) package (note 4). . . . . . . . . . . . . . . . . . . 46 maximum junction temperature (hermetic package or die) . . . 175 o c maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. notes: 3. the package thermal impedance is calculated in accordance with jesd 51-3. 4. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads ---------v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads ---------v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 a cd54hc4059, cd74hc4059 cd54hc4059, cd74hc4059
5 prerequisite for switching speci?ations parameter symbol v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min typ max min typ max pulse width cp t w 2 90 - - 115 - - 135 - - ns 4.5 18 - - 23 - - 27 - - ns 615- -20- -23- -ns setup time k b , k c to cp t su 2 75 - - 95 - - 110 - - ns 4.5 15 - - 19 - - 22 - - ns 613- -16- -19- -ns cp frequency f max 2 5 - - 4 - - 4 - - mhz 4.5 27 - - 22 - - 18 - - mhz 6 32 - - 26 - - 21 - - mhz switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max propagation delay, cp to q t plh , t phl c l = 50pf 2 - - 200 - 250 - 300 ns 4.5 - - 40 - 50 - 60 ns 6 - - 34 - 43 - 51 ns c l = 15pf 5 - 17 - ----ns propagation delay, le to q t plh , t phl c l = 50pf 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns 6 - - 30 - 37 - 45 ns c l = 15pf 5 - 14 - ----ns output transition time t thl , t tlh c l = 50pf 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns cp frequency f max c l = 15pf 5 - 54 - ----mhz input capacitance c i - - - - 10 - 10 - 10 pf power dissipation capacitance (notes 5, 6) c pd - 5-36-----pf notes: 5. c pd is used to determine the dynamic power consumption, per package. 6. p d =c pd v cc 2 f i + c l v cc 2 f o where f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage. cd54hc4059, cd74hc4059 cd54hc4059, cd74hc4059
6 test circuits and waveforms note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 2. hc clock pulse rise and fall times and pulse width figure 3. hc transition times and propagation delay times, combination logic figure 4. hc setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits clock 90% 50% 10% gnd v cc t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = fc l i t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t r c l t f c l gnd v cc gnd v cc 50% 90% 10% gnd clock input data input output set, reset or preset v cc 50% 50% 90% 10% 50% 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) t h(h) cd54hc4059, cd74hc4059 cd54hc4059, cd74hc4059
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 5962-8944501ja active cdip j 24 1 tbd call ti level-nc-nc-nc cd54hc4059f3a active cdip j 24 1 tbd call ti level-nc-nc-nc cd74hc4059e active pdip n 24 15 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hc4059ee4 active pdip n 24 15 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hc4059m96 active soic dw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim CD74HC4059M96E4 active soic dw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 26-sep-2005 addendum-page 1
mechanical data mcdi004a january 1995 revised november 1997 post office box 655303 ? dallas, texas 75265 j (r-gdip-t**) ceramic dual-in-line package 24 pins shown a c 0.018 (0,46) min seating plane 0.010 (0.25) max lens protrusion (lens optional) wide narr wide 32 narr wide 0.125 (3,18) min 0.514(13,06) 0.571(14,50) 0.541(13,74) 0.598(15,19) 1.668(42,37) 1.668(42,37) 1.632(41,45) 1.632(41,45) 0.590(14,99) 0.590(14,99) 0.624(15,85) 0.624(15,85) 4040084/c 10/97 0.012 (0,30) 0.008 (0,20) 40 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 2.032(51,61) 2.032(51,61) 2.068(52,53) 2.068(52,53) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50) b 13 12 0.090 (2,29) 0.060 (1,53) 0.045 (1,14) 0.065 (1,65) 24 1 28 0.022 (0,56) 0.014 (0,36) narr 24 narr wide 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 1.235(31,37) 1.235(31,37) 1.265(32,13) 1.265(32,13) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50) oao dim obo oco pins ** max min min max max min 0.514(13,06) 0.571(14,50) 0.541(13,74) 0.598(15,19) 1.465(37,21) 1.465(37,21) 1.435(36,45) 1.435(36,45) 0.590(14,99) 0.590(14,99) 0.624(15,85) 0.624(15,85) 0.175 (4,45) 0.140 (3,56) 0.100 (2,54) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. window (lens) added to this group of packages (24-, 28-, 32-, 40-pin). d. this package can be hermetically sealed with a ceramic lid using glass frit. e. index point is provided on cap for terminal identification.
mechanical data mpdi006b ? september 2001 ? revised april 2002 post office box 655303 ? dallas, texas 75265 n (r?pdip?t24) plastic dual?in?line 0.020 (0,51) min 0.021 (0,53) 0.015 (0,38) 0.100 (2,54) 1 24 0.070 (1,78) max 12 13 1.222 (31,04) max 0.125 (3,18) min 0??15? 0.010 (0,25) nom 0.425 (10,80) max seating plane 0.200 (5,08) max 0.360 (9,14) max 0.010 (0,25) 4040051?3/d 09/01 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms?010
mechanical data mpdi008 october 1994 post office box 655303 ? dallas, texas 75265 n (r-pdip-t**) plastic dual-in-line package 24 pin shown 12 seating plane 0.560 (14,22) 0.520 (13,21) 13 0.610 (15,49) 0.590 (14,99) 52 48 40 0.125 (3,18) min 2.390 (60,71) (62,23) (53,09) (51,82) 2.040 2.090 2.450 2.650 (67,31) (65,79) 2.590 0.010 (0,25) nom 4040053 / b 04/95 a 0.060 (1,52) typ 1 24 32 28 24 1.230 (31,24) (32,26) (36,83) (35,81) 1.410 1.450 1.270 pins ** dim 0.015 (0,38) 0.021 (0,53) a min a max 1.650 (41,91) (40,89) 1.610 0.020 (0,51) min 0.200 (5,08) max 0.100 (2,54) m 0.010 (0,25) 0 15 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-011 d. falls within jedec ms-015 (32 pin only)

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